DPNOC- 2017 - The 4th International Workshop on Design and Performance of Networks on Chip

Website http://research-uob.com/dpnoc17/ | Edit Freely

Category NOC scalability;Routing protocols;Router microarchitecture;Technology constraints on NoCs; Scheduling and application mapping onto NoC

Deadline: April 20, 2017 | Date: July 24, 2017-July 26, 2017

Venue/Country: Leuven, Belgium

Updated: 2017-04-04 03:08:06 (GMT+9)

Call For Papers - CFP

July 24-26, 2017, Leuven, Belgium

to be held in conjunction with the

The 12th International Conference on Future Networks and Communications

July 24-26, 2017, Leuven, Belgium (http://cs-conferences.acadiau.ca/fnc-17/)

IMPORTANT DATES:

Submission Deadline: April 20, 2017

Authors Notification: May 10, 2017

Final Manuscript Due: May 28, 2017

SCOPE AND OBJECTIVES

The advance in silicon technology has led to the emergence of on-Chip Systems (SoC), where a complete system with a large number of intellectual property cores can be integrated onto a single silicon chip. The performance of SoCs highly depends on the speed and efficiency of their underlying communications subsystems. The light weight networks, known as Network-on-Chip (NoC), have been introduced to overcome the scalability problem found in shared-bus communication architectures. Intensive research studies have been undertaken investigating the design cost, in terms of silicon area and power consumption, and performance of NoC. Most of these studies are targeting NoC topology, router microarchitecture, switching techniques, routing algorithms, and application mapping onto NoC.

The workshop on the Design and Performance of Networks on Chip (DPNoC-2017) will represent an international forum for researchers from both academia and industry to expose the latest trends, research findings, and emerging issues in this area.

The Workshop topics include (but are not limited to) the following:

o Technology constraints on NoCs

o Router microarchitecture

o Flow control techniques

o Switching techniques

o Routing protocols

o Fault tolerance/reliability in NoC

o Scheduling and application mapping onto NoC

o Wireless NoCs

o NOCs modeling and performance evaluation

o NOC scalability

o FPGA-based implementation of reconfigurable NoCs

INSTRUCTIONS FOR PAPER SUBMISSIONS:

You are invited to submit original and unpublished research works on above and other topics related to Design and Performance of Networks on Chip. Submitted papers must not have been published or simultaneously submitted elsewhere. Please, indicate clearly the corresponding author and include up to 6 keywords and an abstract of no more than 400 words.

Paper Format

The submitted paper must be formatted according to the the guidelines of Procedia Computer Science, MS Word Template, Latex, Template Generic, Elsevier.

Paper Length

Submitted papers must be no longer than 6 pages including all figures, tables and references.

Paper Submission

Authors are requested to submit their papers electronically using the The Online EDAS conference management system (https://edas.info/newPaper.php?c=23170) in PDF format.

The submission process will be managed by EDAS. If you have used this system before, you can use the same username and password. If this is your first time using EDAS, you will need to register for an account by clicking "create a new account" button. Upon completion of registration, you will get a notification email from the system and you are ready for submitting your paper. You can upload and re-upload the paper to the system by the submission due date.

Publication

All NoC-2017 accepted papers will be printed in the conference proceedings published by Elsevier Science in the open-access Procedia Computer Science series on-line. Procedia Computer Sciences is hosted on www.Elsevier.com and on Elsevier content platform ScienceDirect (www.sciencedirect.com), and will be freely available worldwide. All papers in Procedia will also be indexed by Thomson Reuters' Conference Proceeding Citation Index http://thomsonreuters.com/conference-proceedings-citation-index/. The papers will contain linked references, XML versions and citable DOI numbers. You will be able to provide a hyperlink to all delegates and direct your conference website visitors to your proceedings. All accepted papers will also be indexed in DBLP (http://dblp.uni-trier.de/).

All accepted papers will be scheduled for oral presentations. At least one author of each accepted paper is required to register and attend the conference to present the work.

Journal Special Issue

Extended version of all accepted papers in the workshop will be published as special issue on The International Journal of Computing and Digital Systems (IJCDS) (http://journals.uob.edu.bh/Pages/PageNotFoundError.aspx?requestUrl=http://journals.uob.edu.bh/computing). Papers must be formatted according to IJCDS format.