ICMTS 2013 - 2013 26Th International Conference On Microelectronic Test Structures

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Category ICMTS 2013

Deadline: September 21, 2012 | Date: March 25, 2013-March 28, 2013

Venue/Country: Osaka, Japan

Updated: 2012-05-19 23:15:38 (GMT+9)

Call For Papers - CFP

University Nakanoshima Center, Osaka, Japan, bringing together designers and users of test

structures to discuss recent developments and future directions. The conference will be held on

March 26-28, 2013, preceded by a one-day Tutorial Short Course on Microelectronic Test Structures

on March 25. There will be an equipment exhibition relating to test structure measurements. Original

papers are solicited presenting new developments in test structures, as well as their implementation

and/or application, related to silicon, semiconductors, nanotechnology and MEMS. A Best Paper

award will be presented by the Technical Program Committee. The conference will be held in

cooperation with the Institute of Electronics, Information and Communication Engineers and, the

Japan Society of Applied Physics, and will be sponsored by the IEEE Electron Devices Society, and

the Association for Promotion of Electrical, Electronic and Information Engineering.

Suggested topics include (but are not limited to):

Material and Process Characterization: Evaluation of wafer start materials (Si, SiGe, strained

silicon, SOI, III-V, II-VI, etc.), dielectrics (high-k gate, low-k interconnect), homoepitaxial and

heteroepitaxial layers. Resistivity, mobility, stress, contact resistance, dielectric, and interconnect

measurements.

Replicated Feature Metrology: Electrical and non-electrical characterization of level-to-level

registration, feature placement, critical dimension, mask and reticle process control.

Manufacturing of Integrated Circuits and MEMS: Evaluation of individual and groups of

integrated circuits, device and MEMS process steps and elements: transistors, diodes, mechanical

structures, device isolation, memory cells and interconnect. Assessment of MMICs, RF components,

3D integration and multi chip packages.

MEMS, NEMS, and Microfluidics: Test structures and methods for evaluating electro-mechanical

devices, such as actuators, sensors, switches, and microfluidic devices.

Large Area Electronics and Emerging Devices: Test structures for evaluating displays, printed /

flexible devices, power devices, photovoltaics, as well as emerging devices, such as organic /

oxide-based / biomolecular / spintronic devices, ReRAMs, nano-structures, and related materials.

Device and Circuit Modeling, Parameter Extraction: Model parameter extraction, RF device

modeling, de-embedding, pulsed measurements, DC / AC / high frequency measurement techniques

and applications.

Reliability Test Structures: Test structures and methods for transistor / thin film / dielectric /

interconnect reliability evaluation, quality assurance, thermal monitoring and analysis, accelerated

wafer level tests, wafer level burn-in, and reliability prediction.

Matching and Variability Test Structures: Mismatch / variability characterization and modeling

of components (transistors, resistors, capacitors, inductors, mechanical components) and circuits.

Technology R&D, Integration, and DFM: Test structures for FEOL or BEOL evaluation, design

rule determination, process uniformity and worst-case analysis, assessment of integration and new

technologies. Calibration of DFM models such as lithography, OPC, CMP, or parametric variation.

Evaluation and optimization of standard cell macros and other product circuits.

Yield Enhancement and Production Process Control: Yield enhancement structures and methods,

yield modeling, statistical process control, defect estimation structures and methods, failure

identification and characterization, many-component / matrix test circuitry for technology assessment,

evaluation of design-manufacturing interactions (DFY).

Test Structure Design Methods: Design flows for automated design, verification strategies, design

for analysis, parameterized design, and related design issues.

Test Structure Utilization Strategy: Test equipment, probing and programmable testing for process

diagnostics, test throughput optimization, database and data analysis methods, statistical data

analysis, expert systems, and related techniques.

Authors are asked to submit an abstract of up to four pages in PDF format (font-embedded). The first

cover page must consist of a title, a 50-words summary, author’s name, the full address, fax number

and e-mail address of the lead author, and author preference for oral or poster session presentation, if

any. The body of the abstract should be of three pages or less consisting of one page text (typically

800 to 1000 words) followed by up to two pages containing major figures and tables. Please visit the

ICMTS official web site http://www.see.ed.ac.uk/ICMTS/ for paper submission.

The selection process will be based on the technical merit and will be highly weighted in favor of

papers that have a high test structure content, include measurement data and analysis together with

illustrations of the test structures involved. Abstracts received by September 21, 2012 will be

considered for the conference. A notice of paper acceptance with instructions for manuscript

preparation for the conference proceedings will be sent to the authors of the papers selected for

presentation by early November, 2012. The deadline for the final paper will be January 14, 2013.

For further technical information, please contact the technical chairman:

Kiyoshi Takeuchi

Renesas Electronics Corp.

kiyoshi.takeuchi.znrenesas.com