HEART 2015 - International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies
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Website http://www.isheart.org/HEART2015/ |
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Category power-efficient;accelerator;FPGA;GPU;heterogeneous architecture;SoC;NoC;
Deadline: March 06, 2015 | Date: June 01, 2015-June 02, 2015
Venue/Country: Boston MA, U.S.A
Updated: 2015-02-19 11:53:08 (GMT+9)
Call For Papers - CFP
HEART2015 (http://www.isheart.org):International Symposium onHighly Efficient Accelerators and Reconfigurable Technologies1-2 June 2015 Boston MA, USAHEART2015 Design Contest (http://lut.eee.u-ryukyu.ac.jp/dc15/)Important dates (Technical Program):- Paper submission due: March 6, 2015 (firm deadline)- Author notification: April 6, 2015- Camera-ready due: April 20, 2015- Symposium Dates: June 1-2, 2015Important dates (Design Contest):- Regular papers due: March 10, 2015- Acceptance Notification (for regular paper submission): April 1, 2015- Camera-ready/Author Registration: April 15, 2015- Abstract submission due: April 1, 2015- Acceptance Notification (for abstract submission): April 15, 2015The Sixth International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART) is a forum to present and discuss new research on accelerators and the use of reconfigurable technologies for high-performance and/or power-efficient computation. Submissions are solicited on a wide variety of topics related to the acceleration for high-performance computation, including but not limited to:Architectures and systems:- Novel systems/platforms for efficient acceleration based on FPGA, GPU, and other devices- Heterogeneous processor architectures and systems for scalable, high-performance, high-reliability, and/or low-power computation- Reconfigurable and configurable hardware and systems including IP-cores, embedded systems, SoCs, and cluster/grid/cloud computing systems for scalable, high-performance and/or low-power processing- Custom computing system for domain-specific applications such as Big-data, multimedia, bioinformatics, cryptography, and more- Novel architectures and device technologies that can be applied to efficient acceleration, including many-core/NoC architectures, 3D-stacking technologies and optical devicesSoftware and applications:- Novel applications of high-performance computing and Big-data processing with efficient acceleration and custom computing- System software, compilers and programming languages for efficient acceleration systems / platforms, including many-core processors, GPUs, FPGAs and other reconfigurable /custom processors- Run-time techniques for acceleration, including Just-in-Time compilation and dynamic partial-reconfiguration- Performance evaluation and analysis for efficient acceleration- High-level synthesis and design methodologies for heterogeneous, reconfigurable and/or custom processors/systemsIn order to encourage open discussion on future directions, the program committee will provide higher priority for papers that present highly innovative and challenging ideas.We are planning to organize special sessions on HPC, Big data, and Dynamic Reconfiguration. When submitting a paper, please select topic(s) if the paper is related to them. Note that regardless of the selection of special session topic(s), your paper will undergo the same peer-review process as the main technical track.As in previous HEART editions, we plan to publish selected accepted papers at HEART 2015 in post-proceedings ACM SIGARCH Computer Architecture News (CAN), which is also available in ACM Digital Library.Prospective authors are invited to submit original and unpublished contributions as 6-page papers to be considered as regular papers or 4-page papers to be considered as poster papers. All contributions must be submitted electronically in PDF format (two columns, US letter size, single-spacing, 10 points for main body text). For double-blind review, manuscripts must NOT identify the authors in any way, so author names, affiliations, e-mail addresses and self-references should be blanked out. Papers that identify authors may be rejected without review. You can submit your contribution(s) by following this easychair submission link.Each accepted paper MUST have at least one author with a regular registration for the manuscript to be included and published in the symposium proceedings and ACM SIGARCH CAN post-proceedings. Authors are also expected to attend and present their paper(s) at the symposium.The HEART2015 paper template can be download from MS-Word: http://www.isheart.org/HEART2015/heart2015.docLatex: http://www.isheart.org/HEART2015/heart2015.clsFPGA Design Contest 2015 (Blocus Duo)- Following the FPGA design competition in HEART2014, we are planning another Blokus Duo design contest. The details of HEART2015 contest regulation has been posted on HEART2015 Web site (http://lut.eee.u-ryukyu.ac.jp/dc15/). If you are interested in the previous contest, please refer to HEART 2014 Design Contest:http://lut.eee.u-ryukyu.ac.jp/dc14/Organizing CommitteeGeneral Co-chairs:Martin Herbordt, Boston University, USMiriam Leeser, Northeastern University, USVice chair:Martin Margala, UMass Lowell, USTechnical program co-chairs:Jason Anderson, University of Toronto, CASuhaib Fahmy, Nanyang Technological University, SGWim Vanderbauwhede, University of Glasgow, UKPublicity co-chairs:David Thomas, Imperial College London, UKYoshiki Yamaguchi, University of Tsukuba, JPPublication co-chairs:Yuichiro Shibata, Nagasaki University, JPDesign contest co-chairs:Yasunori Osana, University of the Ryukyus, JPJames Goebel, Boston University, USLocal arrangement:Gabriella McNevin, Boston University, USTechnical Program Committee (TBD)Jason Anderson, University of Toronto, CASuhaib Fahmy, Nanyang Technological University, SGWim Vanderbauwhede, University of Glasgow, UKSai Rahul Chalamalasetti, Hewlett Packard, USRay C.C. Cheung, City University of Hong Kong, HKFlorent de Dinechin, INSA Lyon, FRDiana Goehringer, Ruhr-University Bochum, DEGary Grewal, University of Guelph, CAToshihiro Hanawa, University of Tokyo, JPYuko Hara-Azumi, Tokyo Institute of Technology, JPMasanori Hashimoto, Osaka University, JPBrad L. Hutchings, Brigham Young University, USTomonori Izumi, Ritsumeikan University, JPPeter Andrew Jamieson, Miami University, USNachiket Kapre, Nanyang Technological University, SGChristos Kartsaklis, Oak Ridge National Labs, USKenneth Kent, University of New Brunswick, CAJoo-Young Kim, Microsoft Research, USDirk Koch, University of Manchester, UKHerman Lam, University of Florida, USPhilip Leong, University of Sydney, AUTsutomu Maruyama, University of Tsukuba, JPSmail Niar, University of Valenciennes, FRGregory D. Peterson, University of Tennessee, USSoojung Ryu, Samsung Advanced Institute of Technology, KRKentaro Sano, Tohoku University, JPHayden Kwok-Hay So, University of Hong Kong, HKIoannis Sourdis, Chalmers University of Technology , SEHenry Styles, Xilinx, USBharat Sukhwani, IBM Thomas J. Watson Research Center, USHiroyuki Takizawa, Tohoku University, JPDavid Thomas, Imperial College, London, UKVivek Venugopal, United Technologies Research Center, USTao Wang, Peking University, CNYu Wang, Tsinghua University, CNMinoru Watanabe, Shizuoka University, JPStephan Wong, Delft University of Technology, NLYoshiki Yamaguchi, University of Tsukuba, JPMasato Yoshimi, University of Electro-Communications, JP
Keywords: Accepted papers list. Acceptance Rate. EI Compendex. Engineering Index. ISTP index. ISI index. Impact Factor.
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