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    NANOARCH 2012 - IEEE/ACM International Symposium on Nanoscale Architectures

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    Website www.nanoarch.org | Want to Edit it Edit Freely

    Category NANOARCH 2012

    Deadline: April 10, 2012 | Date: July 04, 2012-July 06, 2012

    Venue/Country: Amsterdam, Netherlands

    Updated: 2012-01-12 16:04:52 (GMT+9)

    Call For Papers - CFP

    NANOARCH is the annual cross-disciplinary forum for the discussion of novel post-CMOS nanocomputing directions and emerging nanoscale CMOS. The symposium seeks papers on innovative ideas for solutions to the principal challenge facing integrated electronics in the 21st century - how to design, fabricate, and integrate nanosystems to overcome the fundamental limitations of CMOS. In particular, such systems could (1) contain unconventional nanodevices with unique capabilities, including directions beyond simple switches, (2) introduce new logic and memory concepts, (3) involve novel circuit styles, (4) introduce new concepts for computing, (5) reconfigure and/or mask faults at much higher rates than in CMOS, (6) involve new paradigms for manufacturing, and (7) rethink the methodologies and design tools involved.

    This symposium includes several exciting sessions and opportunities for interaction. In addition to Regular papers presenting original techniques / directions, it invites the community to also submit Nanofabric Progress Updates giving a progress update of their nanofabrics directions to date across devices, circuits, architecture and manufacturability aspects - e.g. 2D/3D nanowire, magnonic, memristor, CNT, graphene, FinFETs, and QCA based directions.

    In addition, Crosscut papers are invited from the broader nanotechnology community to highlight promising nanomaterial, nanodevice, nanomanufacturing, and integration ideas with application potential in nanoscale architectures.

    Example topics (both theoretical and experimental) of interest include (but are not limited to):

    Novel nanodevices and manufacturing/integration ideas with a focus on nanoarchitectures

    Nanoelectronic circuits, nanofabrics, computing paradigms and nanoarchitectures

    2D/3D/hybrid nanodevice integration and manufacturing, with variability, defect and fault tolerance

    Nanodevice and nanocircuit models, methodologies and computer aided design tools

    Fundamental limits of computing at the nanoscale

    We sincerely hope you can participate in NANOARCH 2012. Should you have any questions, please contact us using the links to the left (if not functional will be updated shortly with more details).

    Proceedings from the previous NANOARCH symposiums are available online at IEEE Xplore

    Final versions of accepted papers will be included in official NANOARCH 2012 symposium proceedings, and Special Issues in IEEE Transactions on Nanotechnology and Special Issue on Future Technologies for Computers, Elsevier Journal of Parallel and Distributed Computing.

    Keywords: Accepted papers list. Acceptance Rate. EI Compendex. Engineering Index. ISTP index. ISI index. Impact Factor.
    Disclaimer: ourGlocal is an open academical resource system, which anyone can edit or update. Usually, journal information updated by us, journal managers or others. So the information is old or wrong now. Specially, impact factor is changing every year. Even it was correct when updated, it may have been changed now. So please go to Thomson Reuters to confirm latest value about Journal impact factor.