SOC 2011 - Workshop on Low Power System on Chip (SoC)

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SOC 2011 - Workshop on Low Power System on Chip (SoC)

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Category SOC 2011

Deadline: April 25, 2011 | Date: July 25, 2011

Venue/Country: Florida, U.S.A

Updated: 2011-03-29 13:49:02 (GMT+9)

Call For Papers - CFP

As a part of the IEEE International Green Computing conference, a special workshop on low power System on Chip (SoC) will be organized. This workshop will address various aspects of designing power efficient SoC and low power SoC test. The continuing progress in silicon technologies and integration levels is producing complete end-user systems on a single chip. Design technologies in this massive integration era will present unprecedented advantages and challenges, the former being related to very high device densities and the latter to soaring power dissipation issues. Reducing on-chip power consumption has become a critical issue for the ultra-deep submicron/nanotechnology regime. Design of a low-power SoC involves adopting various strategies at different levels of abstraction. Starting from overall architecture, choice of processors and memory blocks, target technology, I/O, place & route strategy, circuit design styles everything influence design of a power efficient SoC. Moreover, in the emerging multi-core SoC domain, roles of power efficient interconnects and data routing protocols are very important. Above all, the recent development of complex, high-performance, low-power devices implemented in deep-submicron technologies creates a new class of more sophisticated electronic products, which makes power management a critical parameter that SoC engineers cannot ignore during both design and test development.

This workshop will encompass a broad range of topics related to low power SoC design and test. Its objective is to facilitate exchange of valuable information and ideas among a wide spectrum of researchers. The workshop will consist of invited presentations and contributed peer-reviewed research papers. The topics of interest include, but are not limited to, the following:

Low power SoC architecture

Low power processor design

I/O design

Clock routing

Power efficient circuit design

Low power memory design

Low power and high speed wireless transceiver design

Energy efficient multi-core architectures and Network-on-Chip

Emerging interconnect technologies, like on-chip photonic, RF and wireless interconnects.

Low power coding methods for SoCs

Low power SoC test

http://school.eecs.wsu.edu/LPSoC

Keywords: Accepted papers list. Acceptance Rate. EI Compendex. Engineering Index. ISTP index. ISI index. Impact Factor.
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