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RASDAT 2012 - 3rd IEEE International Workshop on Reliability Aware System Design and Test (RASDAT12)
Category RASDAT 2012
Deadline: September 26, 2011 | Date: January 07, 2012-January 08, 2012
Venue/Country: Hyderabad, India
Updated: 2011-05-02 10:47:38 (GMT+9)
Call For Papers - CFP
Even as advances in CMOS technology come up against physical limits of material properties and lithography, raising many new challenges that must be overcome to ensure IC quality and reliability, there appears to be no obvious alternate technology that can replace End-of-Roadmap CMOS over the next decade. However, many reliability challenges from increasing defect rates, manufacturing variations, soft errors, wearout, etc. will need to be addressed by innovative new design and test methodologies if device scaling is to continue on track as per Moore`s Law to 10nm and beyond. The key objective of this annual workshop, planned to be held in conjunction with the International Conference on VLSI Design, is to provide an informal forum for vigorous creative discussion and debate of this area. The aim is to encourage the presentation and discussion of truly innovative and `out-of-the-box` ideas that may not yet have been fully developed for presentation at reviewed conferences to address these challenges. Additionally, the workshop invites embedded talks and tutorials on cutting edge topics related to reliability aware design of CMOS and hybrid nanotechnology systems.http://www.serc.iisc.ernet.in/~viren/RASDAT12/
Representative topics include, but are not limited to:-Design for test,- Built-in self-test- ATPG and defect oriented test- Delay test- Low power test- Instruction-based self-test- On-line test methodology- Reliability of CMOS circuits- Self checker circuits- Self diagnosis methods- Fault tolerant micro-architecture- Self-healing system design- Energy and performance aware fault tolerant micro-architectures- Device degradation and mitigation- System validation methodology- Secure system design- Design for reliability, dependability, and verifiabilitySubmissionsAuthors are invited to submit previously unpublished technical proposals. The proposals must be full papers not to exceed 6 pages. Each submission should include: title, full name and affiliation of all authors, a short abstract of 50 words, and 4 to 6 keywords. Also, identify a contact author and include a complete correspondence address, phone number, fax number, and e-mail address. Submit a copy of your proposal in PDF either online submission or via e-mail to : rasdat2012
serc.iisc.ernet.inKey Dates:Paper Submission: September 26, 2011Acceptance Notification: October 31, 2011Final Paper Due: December 1, 2011Presentation Due: Jan 1, 2012General InformationAdit SinghAuburn University, Auburn, USAE-mail: adsinghauburn.eduTel: +1.334.644.1647Fax: +1.334.844.1809Virendra SinghIndian Institute of Science, Bangalore, IndiaE-mail: virenserc.iisc.ernet.inVirendracomputer.orgTel: +91.80.2293.3421Fax: +91.80.2360.2648Program Related InformationErik LarssonLinkoping University, SwedenE-mail: erilaida.liu.eduTel: +46.13.28.6619Fax: +46.13.28.4499Rubin ParekhjiTexas Instruments, Bangalore, IndiaE-mail: parekhjiti.comKeywords: Accepted papers list. Acceptance Rate. EI Compendex. Engineering Index. ISTP index. ISI index. Impact Factor.
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