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    MTV 2011 - 2011 12th International Workshop on Microprocessor Test and Verification (MTV)

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    Website mtvcon.org | Want to Edit it Edit Freely

    Category MTV 2011

    Deadline: September 01, 2011 | Date: December 05, 2011-December 07, 2011

    Venue/Country: Austin, U.S.A

    Updated: 2011-05-27 06:48:47 (GMT+9)

    Call For Papers - CFP

    The 12th annual workshop on Microprocessor Test and Verification will be held on December 5th through 7th, 2011 in Austin, TX. There will also be a coinciding DVClub event on December 7th at Cool River Cafe.

    General Chair: Magdy S. Abadir, Freescale Semiconductor

    Program Co-Chair: Jay Bhadra, Freescale Semiconductor

    Program Co-Chair: Li-C. Wang, University of California at Santa Barbara

    Scope

    The purpose of MTV is to bring researchers and practitioners from the fields of verification and test together to exchange innovative ideas and to develop new methodologies to solve the difficult challenges facing us today in various processor and SOC design environments. In the past few years, some work has been done on exploiting techniques from test to solve problems in verification and vice versa. This is the 12th edition of the MTV Workshop, a testament to its success in providing an ideal environment for cross-examination of test and verification experiences and innovative solutions.

    Areas of Interest include

    Validation of microprocessors and SOCs

    Experiences on test and verification of high performance processors and SOCs

    Test/verification of multimedia processors and SOCs

    Performance testing

    High-level test generation for functional verification

    Emulation techniques

    Silicon debugging

    Low Power verification

    Formal techniques and their applications

    Verification coverage

    Test generation at the transistor level

    Equivalence checking of custom circuits at the transistor level

    ESL Methodology

    Virtual Platforms

    Software verification

    Circuit level verification

    Switch-level circuit modeling

    Timing verification techniques

    Path analysis for verification or test

    Design error models

    Design error diagnosis

    Design for testability or verifiability

    Optimizing SAT procedures for application to testing and formal verification


    Keywords: Accepted papers list. Acceptance Rate. EI Compendex. Engineering Index. ISTP index. ISI index. Impact Factor.
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