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    CASS 2012 - The 2nd Workshop on Communication Architecture for Scalable Systems CASS 2012

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    Website www.ipdps.org/ipdps2012/2012_workshops.html | Want to Edit it Edit Freely

    Category CASS 2012

    Deadline: December 03, 2011 | Date: May 21, 2012-May 25, 2012

    Venue/Country: Shanghai, China

    Updated: 2011-09-29 16:30:49 (GMT+9)

    Call For Papers - CFP

    High-speed communication is critical to all parts of an HPC system. On-chip networks for emerging many-core processors; point-to-point interconnects, which have replaced the system bus for intra-node communication; and system-wide networks, which form the backbone of any large-scale parallel system, all contribute to the construction of the world’s fastest computers. Numerous research groups in academia, industry, and government are currently investigating the issues involved in improving the speed, reliability, power consumption, and other characteristics of communication subsystems and seeking new ways to advance the state of the art in cluster communication.

    The goal of this workshop is to bring together researchers working on improving communication at every level of the network hierarchy (on-chip, intra-node, and cross-cluster), thereby enabling the sharing and adaptation of ideas from what have traditionally been separate communities.

    All researchers and practitioners working in the area of communication architectures for scalable systems are encouraged to submit a paper to the workshop.

    Topics of Interest

    Topics of interest for the workshop include but are not limited to the following:

    Hardware and software issues related to router/switch organization, flow control, collective communication, congestion control, routing and deadlock handling, network topology, load balancing, reliability, QoS support, topology discovery, dynamic reconfiguration, energy efficiency, and clustered storage and fileservers. Research at any level of the network hierarchy (on-chip, intra-node, and cross-cluster) is welcome.

    Architectural and run-time system support for messaging, PGAS, shared memory, and other programming models

    Design and implementation of standard or custom software communication layers for any or all parts of the network hierarchy

    Papers covering more than one of on-chip, intra-node, and cluster-wide communication networks are especially sought. Results of both theoretical and practical significance will be considered. Note, however, that papers on topics that are too far removed from scalable communication in HPC systems (e.g., mobile networks, intrusion detection, peer-to-peer networks, Grid/cloud computing) will be rejected without review.


    Keywords: Accepted papers list. Acceptance Rate. EI Compendex. Engineering Index. ISTP index. ISI index. Impact Factor.
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