HIPEAC 2010 - 5th International Conference on High Performance and Embedded Architectures and Compilers (HiPEAC'2010)

Website http://www.hipeac.net/conference/ | Edit Freely

Category HIPEAC 2010

Deadline: November 13, 2009 | Date: January 25, 2010

Venue/Country: Pisa, Italy

Updated: 2010-06-04 19:32:22 (GMT+9)

Call For Papers - CFP

The 5th International Conference on

High Performance and Embedded Architectures and Compilers

Pisa, ITALY, January 25-27, 2010

C A L L F O R P A P E R S

IMPORTANT DATES

Abstract due: July 3 (11.59 PM, PDT), 2009

Paper due: July 10 (11.59 PM, PDT), 2009

SCOPE

The challenges faced by the high-performance general-purpose and

embedded worlds are converging. The embedded market evolves rapidly,

quickly expanding the capabilities of new devices, and the

requirements of these new applications demand technologies that not

long ago were in the realm of high-performance computing. Conversely,

the energy and cost constraints typical of the embedded world are now

also among the most important design criteria for general purpose

computing systems. Because performance no longer automatically

increases with advances in semiconductor technology, it has become

essential to discover new paths to optimize performance, energy and

cost across software and hardware.

The HiPEAC conference provides a forum for computer and compiler

architects in the field of high performance architecture and

compilation for embedded and general-purpose systems, with a special

emphasis on cross-cutting research that can be applied to both. The

conference aims at the dissemination of advanced scientific knowledge

and the promotion of international contacts among scientists from

academia and industry.

TOPICS

Topics of interest include, but are not limited to:

* Processor architecture and instruction-level parallelism

* Multi- and many-core architectures (e.g., homogeneous, heterogeneous

MPSoC)

* Memory system design and optimization

* Power, performance and cost efficient processor designs

* Domain specific architectures (e.g., Network, Security or Graphics

processors)

* Interconnection Networks

* Application specific architectures, ASIPs, accelerators, customized

processors

* Reconfigurable architectures and tools for reconfigurable computing

* Compilation techniques for embedded processors

* Dynamic, adaptive and continuous optimization and compilation

* Back-end code generation and scheduling

* Binary translation and optimization

* Compilation and runtime support for multi- and many-core

architectures

* Tools and techniques for simulation and performance analysis

* Program and workload characterization and profiling techniques

* Tools for analysis, design, testing and implementation of embedded

systems

SUBMISSION

Preferably by July 3, 2009, submit an electronic copy of your paper

(in PDF) not exceeding 16 pages and 5,000 words, as explained at:

http://www.hipeac.net/conference

We will follow the Springer LNCS rules for accepted papers, as

explained in the Springer LNCS web site

http://www.springer.com/computer/lncs

where Authors can also find the instructions for final paper

formatting, using different text editors, from LaTeX, to Word, to

FrameMaker, and other instructions regarding Copyright Forms, etc.

Please be aware that Authors will need to submit all source files,

including LaTeX files, and Word documents, and the final PDF file for

their papers.

Sponsored by:

- HiPEAC Network of Excellence

- University of Pisa

- 7th Framework Programme

GENERAL CHAIRS

Yale N. Patt, UT Austin, USA

Pierfrancesco Foglia, Universita' di Pisa, Italy

PROGRAM CHAIRS

Paolo Faraboschi, HP Labs

Evelyn Duesterwald, IBM Research

PROGRAM COMMITTEE

Erik Altman, IBM

Albert Cohen, INRIA Saclay

Jesus Corbal, Intel

Jack Davidson, University of Virginia

Koen De Bosschere, Ghent University

Jim Dehnert, Google, Inc.

Giuseppe Desoli, STMicroelectronics

Pedro C. Diniz, Tech. Univ. of Lisbon (IST)/INESC-ID

Carol Eidt, Microsoft

Babak Falsafi, EPFL

Georgi Gaydadjiev, TU Delft

Thomas Gross, ETH Zurich

Rajiv Gupta, Univ. of California, Riverside

Mary Jane Irwin, Penn State University

Wolfgang Karl, Karlsruhe Institute of Technology

Josep Llosa, UPC

Scott Mahlke, University of Michigan

Sally A. McKee, Chalmers University of Technology

Avi Mendelson, Microsoft Israel

Michael O'Boyle, University of Edinburgh

Daniel Ortega, HP Labs

Emre Ozer, ARM

Keshav Pingali, UT Austin

Milos Prvulovic, Georgia Tech

Cristina Silvano, Politecnico di Milano

David Whalley, Florida State University

Donald Yeung, University of Maryland

WORKSHOP/TUTORIAL CHAIR

Sandro Bartolini, Universita' di Siena, Italy

FINANCE CHAIR

Wouter De Raeve

Ghent University, Belgium

PUBLICITY CHAIR

Roberto Giorgi, Universita' di Siena, Italy

PUBLICATION CHAIR

Xavier Martorell, BSC, Spain

SUBMISSION CHAIR

Michiel Ronsse, Ghent University, Belgium

WEB CHAIR

Klaas Millet, Ghent University, Belgium

STEERING COMMITTEE

Anant Agarwal, MIT, USA

Koen De Bosschere, Ghent University, Belgium

Joel Emer, Intel, USA

Wen-mei W. Hwu, UIUC, USA

Margaret Martonosi, Princeton University, USA

Michael O'Boyle, University of Edinburgh, U.K.

Andre' Seznec, IRISA, France

Per Stenstrom, Chalmers University, Sweden

Theo Ungerer, University of Augsburg, Germany

Mateo Valero, UPC, Spain