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APSS 2010 - The First IEEE International Workshop on Architecting Parallel Software Systems (APSS 2010)
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Website compsac.cs.iastate.edu |
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Category APSS 2010
Deadline: March 01, 2010 | Date: July 19, 2010
Venue/Country: Seoul, South Korea
Updated: 2010-06-04 19:32:22 (GMT+9)
Call For Papers - CFP
The First IEEE International Workshop on Architecting Parallel Software Systems (APSS 2010)Held in conjunction with COMPSAC, the IEEE Signature Conference on Computers, Software, and Applications. COMPSAC 2010 will be held in Seoul, Korea, July 19-23.
The theme of APSS 2010 is Parallelizability as an Architectural Software System Aspect.
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Invited Participants
Important Dates
Paper Submission
Computing hardware is increasingly becoming a multi-core, multi-processor execution environment, but most software is developed according to serial computer programming paradigms. There is a pressing need for software development paradigms that hide the complexity of parallelism on the programming level. In addition to newly developed code targeting parallel computing platforms, a growing amount of legacy serial code needs to be prepared for parallelism as well. Most developers have experience in serial programming and prefer to use serial programming paradigms (one reason being that parallel programming is substantially more complicated to master than serial programming). Hiding parallelism on the programming level would allow developers to unlock the potential of today's parallel computing platforms, but without having to become parallel programmers.
Parallel computing, from a software engineering point of view, has often a strong focus on the programming level - the programmer uses compiler directives to manually identify pieces of code that are suitable for parallel execution. This workshop aims to promote ideas that address parallel computing as a software system aspect on the architectural level rather than as a code construct on the programming level. Submitted papers should set forth novel ideas that address parallelism from a holistic, architectural perspective and give rise to discussion in the context of the workshop theme.
The APSS workshop provides a forum for all topics related to parallel software system development from an architectural perspective. Researchers and practitioners alike are invited to present and discuss novel concepts, recent results (e.g., proof-of-concept examples in Google Go or Erlang), problems, approaches and methodologies, tools and techniques or any bold idea that may help in defining parallelizability as an architectural aspect in software system engineering. The workshop will have an open and informal character to encourage interaction, discussions and feedback.
Topics of interest include, but are not limited to:
Parallelizability as an architectural aspect in software system engineering
Physical and temporal software and hardware resource handling on the architectural level
Expressing parallelizability (visualization, notation, etc.)
Combining parallel and serial parallel programming paradigms
Preparing serial code bases for parallelism
Testing, verification and validation of parallel software systems
Overall parallel software system development
Invited Participants
Likely participants are from academia or industry with an interest in software system development trying to find solutions to (1) preparing legacy serial code for parallelism and (2) developing parallel software systems, preferably using existing serial programming paradigms whenever possible. This workshop is particularly useful for young researchers who would like to present their work and receive feedback from an experienced community with a strong track record in software engineering research and embedded system development.
Important Dates
March 1, 2010: Paper submission due
March 30, 2010: Paper notification
Apr 30, 2010: Final manuscript due
Paper Submission
Papers must be submitted electronically via the APSS 2010 Submission Page (available through the link below). Manuscripts will be limited to six pages including all figures, tables, and references. Extra page charges may apply. The format of submitted papers must follow the IEEE conference proceedings guidelines (i.e., 8.5" x 11", two-column format) available from
Keywords: Accepted papers list. Acceptance Rate. EI Compendex. Engineering Index. ISTP index. ISI index. Impact Factor.
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