DPNOC 2016 - The 3rd International Workshop on Design and Performance of Networks on Chip

Website http://www.intnoc.org/dpnoc16/ | Edit Freely

Category On-chip Networks; Router microarchitecture; NOCs modeling and performance evaluation; FPGA-based implementation of reconfigurable NoCs

Deadline: May 31, 2016 | Date: August 15, 2016-August 18, 2016

Venue/Country: Montreal, Canada

Updated: 2016-05-20 19:41:41 (GMT+9)

Call For Papers - CFP

15-18 August 2016, Montreal, Canada

http://www.intnoc.org/dpnoc16/

in conjunction with the 11th International Conference on Future Networks and Communications (FNC 2016) (http://cs-conferences.acadiau.ca/fnc-16/)

IMPORTANT DATES:

Submission Deadline: May 31, 2016

Final Manuscript Due: June 14, 2016

SCOPE AND OBJECTIVES

The advance in silicon technology has led to the emergence of on-Chip Systems (SoC), where a complete system with a large number of intellectual property cores can be integrated onto a single silicon chip. The performance of SoCs highly depends on the speed and efficiency of their underlying communications subsystems. The light weight networks, known as Network-on-Chip (NoC), have been introduced to overcome the scalability problem found in shared-bus communication architectures. Intensive research studies have been undertaken investigating the design cost, in terms of silicon area and power consumption, and performance of NoC. Most of these studies are targeting NoC topology, router microarchitecture, switching techniques, routing algorithms, and application mapping onto NoC.

The workshop on the Design and Performance of Networks on Chip (DPNoC'2015) will represent an international forum for researchers from both academia and industry to expose the latest trends, research findings, and emerging issues in this area.

The Workshop topics include (but are not limited to) the following:

o Technology constraints on NoCs

o Router microarchitecture

o Flow control techniques

o Switching techniques

o Routing protocols

o Fault tolerance/reliability in NoC

o Technology constraints on NoCs

o Scheduling and application mapping onto NoC

o Wireless NoCs

o NOCs modeling and performance evaluation

o NOC scalability

o FPGA-based implementation of reconfigurable NoCs

INSTRUCTIONS FOR PAPER SUBMISSIONS:

You are invited to submit original and unpublished research works on above and other topics related to Design and Performance of Networks on Chip. Submitted papers must not have been published or simultaneously submitted elsewhere. Please, indicate clearly the corresponding author and include up to 6 keywords and an abstract of no more than 400 words.

Publication: All NoC-2015 accepted papers will be printed in the conference proceedings published by Elsevier Science in the open-access Procedia Computer Science series on-line. Procedia Computer Sciences is hosted on www.Elsevier.com and on Elsevier content platform ScienceDirect (www.sciencedirect.com), and will be freely available worldwide. All papers in Procedia will also be indexed by Thomson Reuters' Conference Proceeding Citation Indexhttp://thomsonreuters.com/conference-proceedings-citation-index/. The papers will contain linked references, XML versions and citable DOI numbers. You will be able to provide a hyperlink to all delegates and direct your conference website visitors to your proceedings. All accepted papers will also be indexed in DBLP (http://dblp.uni-trier.de/).

Journal Special Issue

Extended version of all accepted papers in the workshop will be published as special issue on The International Journal of Computing and Digital Systems (IJCDS) (http://journals.uob.edu.bh/Pages/PageNotFoundError.aspx?requestUrl=http://journals.uob.edu.bh/computing)