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3D-TEST 2010 - 2010 First IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-Test)
Website 3dtest.tttc-events.org |
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Category 3D-TEST 2010
Deadline: August 23, 2010 | Date: November 04, 2010-November 05, 2010
Venue/Country: Austin, U.S.A
Updated: 2010-08-22 03:00:52 (GMT+9)
Call For Papers - CFP
The new 3D-TEST Workshop focuses exclusively on test of and design-for-test for three-dimensional stacked ICs (3D-SICs), including Systems-in-Package (SiP), Package-on-Package (PoP), and especially 3D-SICs based on Through-Silicon Vias (TSVs). While 3D-SICs offer many attractive advantages with respect to heterogeneous integration, smaller form-factor, higher bandwidth and performance, and lower power dissipation, there are many open issues with respect to testing such products. The 3D-TEST Workshop offers a forum to present and discuss these challenges and (emerging) solutions among researchers and practitioners alike.3D-TEST will take place in conjunction with the IEEE International Test Conference (ITC) and is sponsored by the Test Technology Technical Council (TTTC) of the IEEE Computer Society.Topic Areas - You are invited to participate and submit your contributions to the 3D-TEST Workshop. The workshop's areas of interest include (but are not limited to) the following topics:Defects due to Wafer ThinningDefects in Intra-Stack InterconnectsDfT Architectures for 3D-SICsEDA Design-to-Test Flow for 3D-SICsFailure Analysis for 3D-SICsKnown-Good Die / Stack TestingPre-Bond and Post-Bond TestingReliability of 3D-SICsStandardization for 3D TestingSystem/Board Test Issues for 3D-SICsTest Cost Modeling for 3D-SICsTest Flow Optimization for 3D-SICsTester Architecture incl. ATE and BISTThermal/Mechanical Stress in 3D-SICsTSV Test, Redundancy, and RepairWafer Probing and Probe Damage of 3D-SICsSubmission Instructions - Submissions must be sent in as PDF file. The Workshop prefers Full Paper submissions (of up to six pages), but also allows Extended Abstract submissions (of at least two pages). Detailed submission instructions can be found here. All submissions will be evaluated for selection with respect to their suitability for the workshop, originality, technical soundness, and presented results. Selected submissions can be accepted for regular or poster presentation at the Workshop.Publications - The workshop will make available to all participants an Electronic Workshop Digest, which includes all material that authors are willing to provide: abstract, paper, slides, poster, etc. A selected subset of papers will be invited to submit an extended journal version of their manuscript for inclusion in a Special Issue of Springer's 'Journal of Electronic Testing - Theory and Applications' (JETTA), being planned for 2011. Key DatesSubmission deadline : August 23, 2010Notification of acceptance : October 1, 2010Camera-ready material : October 22, 2010Further InformationYervant Zorian - General ChairVirage Logic47100 Bayside ParkwayFremont, CA 94538, USATel.: +1 (510) 360-8035Fax: +1 (510) 360-8078E-mail: yervant.zorian
viragelogic.comErik Jan Marinissen - Program ChairIMEC vzwKapeldreef 75B-3001 Leuven, BelgiumTel.: +32 (0)16 28-8755Fax: +32 (0)16 28-1515E-mail: erik.jan.marinissenimec.beKeywords: Accepted papers list. Acceptance Rate. EI Compendex. Engineering Index. ISTP index. ISI index. Impact Factor.
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