IITC 2011 - 2011 IEEE International Interconnect Technology Conference - IITC

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Category IITC 2011

Deadline: January 07, 2011 | Date: May 08, 2011-May 12, 2011

Venue/Country: Dresden, Germany

Updated: 2010-10-24 15:40:31 (GMT+9)

Call For Papers - CFP

CONFERENCE FORMAT:

Technical Papers: Contributed papers addressing all aspects of interconnect technology (Materials and Unit Processes; Process Integration for Logic or Memory; Process Control/Modeling for Manufacturing; Reliability; TSV and 3D Integration; Optical Interconnect, Interconnect Systems; Packaging; and Novel Materials and Concepts) will be rigorously reviewed. Papers will be selected for either oral or poster presentation.

Regular papers, with 3-page abstracts will be selected for either oral or poster presentation. The Organizing Committee explicitly solicits contributions for new areas: 3D, memory, manufacturing, packaging, optical interconnect and new materials/concepts.

In addition, papers with 2-page abstracts will be selected for a special poster session for New Engineers and Students.

Exhibits/Seminars: New products, processes, analytical methods and materials will be exhibited at the conference. Supplier seminars will be held on the 1st and 2nd evenings of the conference. Please contact the Conference Headquarters for details.

Short Course:

SUBMISSION OF PAPERS:

Deadline: TBD

NOTE: Submission of an abstract for review and subsequent acceptance is considered by the committee as an agreement that the work will not be placed in the public domain by the author prior to the conference. Accepted papers or significant portions of the work may not be placed in the public domain prior to the conference. Violation will be grounds for automatic withdrawal of the paper by the conference committee. Inclusion of materials from publications by other authors may be done only with their expressed permission and with a citation associated with the reproduced material. Appropriate company or government clearance must be obtained by the authors before submission and an IEEE Copyright Form will be required. Submitted papers will not be returned to the authors.

Oral presentations will be 20 minutes in length followed by a 5 minute question period. Poster authors will be required to be at their presentations for a 2-hour period on the day of their poster display.

Papers must be submitted electronically -- Details coming soon. Do not email or mail hard copies to the conference office. Please read the paper preparation and submission guidelines before preparing your paper. In order for your paper to receive a full review, the following information MUST be entered on the website along with your submission:

Title of paper

First author name with complete mailing address, phone, fax and email address

Names, affiliations, city state or country of additional authors

Person to whom correspondence should be sent, if other than the first author

Identification as invited or student paper

Suggestions for up to three potential conference sessions for the paper. See Subjects of Interest

ACCEPTED PAPERS WILL BE PRINTED IN THE PROCEEDINGS WITHOUT THE OPPORTUNITY FOR FURTHER CHANGE. Papers length inclusive of all illustrations, charts and tables must be 3 pages for regular oral/poster sessonis, and 2 pages for special poster sessions for New Engineers and Students, respectively. Contact information for each author must be listed on the first page of the paper: name, affiliation, city, state or country. Authors of accepted papers will be notified by TBD.

Note: Accepted papers may be used for publicity purposes and portions of these papers may be quoted in pre-conference magazine articles and also via the Web. If this is NOT acceptable, authors must indicate this on the Paper Submission site when submitting the paper for review.

2010 SUBJECTS OF INTEREST and PRELIMINARY SESSION TITLES:

IITC New Directions - INTERCONNECT TO INTERCONNECTIONS AND INTERFACES FOR "More Moore" and "More than Moore" Technologies

Materials and Unit Processes

Dielectric materials (low k, ARC, Cap, ESL, etc.) and associated deposition processes (vapor deposition, spin-on, etc.)

Metallization processes/equipment (PVD, CVD, ALD, electroplating, etc.)

Planarization processes for dielectrics and metals, equipment and metrology issues. Alternative planarization techniques

Interconnect specific patterning processes (lithography, etch, etc.) including wet/dry strip and cleaning

Novel or improved tools for metrology and characterization applicable to interconect

Process Integration for Logic or Memory:

Multilevel interconnect processes, clustered processes, novel interconnect structures, contact/via integration, metal barrier and materials interface issues, etc.

Integration processes and issues specific to logic or memory

Across-generation manufacturing science

Reliability

Metal electromigration and stress voiding

Dielectric integrity and mechanical stability, thermal effects, passivation issues

Interconnect reliability prediction/modeling

Chip-package interaction

Advanced Interconnect and Systems Interconnections

New device architectures: Multi-core Technology - impact on packaging and interconnect scaling

Interconnect performance modeling and high frequency characterization of interconnect system integration

Advanced interconnect concepts (optical, superconductors, RF, Interconnects from CPU to system components, etc.).

Heterogeneous Integration: III-V/Ge/C on Si

Embedded Systems (Sensor; Engergy Generation; Harvesting and Storage)

RF and high frequency passive components

TSV and 3D Integration

Materials

3D Design & modeling

TSV etching, barrier deposition electroplating processes

Wafer bonding schemes

Process integration

Reliability issues

Applications

Back-End Memories

Memory Materials like Phase Change Memory (PCM), Resistive RAM (RRAM), Conductive Bridge RAM (CB-RAM) and Magnetoresistive RAM (MRAM)

Concepts for select devices like diodes, MOSFETs, BJTs. Integration of these devices in 2D and monolithically stacked 3D arrays.

Architectures for chips with the above memory materials

Monolithic 3D stacking of NAND flash memory and DRAM

Packaging

Thermal management technology

Green technology (Sn-based solder, Cu-pillar, etc.)

Flip-chip, wafer level packaging, chip-on-chip, MCM, etc.)

Noval board level interconnect, package architectures

Packaging optimization and design for low-k dielectrics

Interconnect structures for strengthening low-k/Cu film stacks

Seal ring and bond/bump pad design

Novel Materials and Concepts

Advanced interconnect concepts, options and issues for post-SiCMOS devices

Emerging interconnect materials: critical materials issues and parameters for implementation (e.g.Carbon Technology; Nanowires; Nano-Materials)

Interface connections (Si-Si; Organic-Organic; Hybrid)

Interconnects for novel non-volatile, embedded memories (PCM, resistive, etc.)

Interconnects for display, PV and flexible devices

Interconnects for optical applications

Interconnect/metallization issues in MEMs and bio devices

SUBMIT YOUR PAPER

LATE NEWS PAPERS:

Deadline: TBD

A very limited number of papers reporting the latest breakthroughs may be accepted as late news papers. Prospective authors should email (iitchis.com) a pdf file (REMEMBER to "embed all fonts") of the paper. The paper must be two pages in length inclusive of illustrations, charts and tables. Paper format must adhere to the guidelines described in the Author's Kit. Accepted late news papers will be presented orally for 10 minutes followed by a 5 minute question period. Late news papers will be printed in the conference proceedings but will not be included in the advance program. An IEEE copyright form will be required.

GENERAL INFORMATION:

For additional information, including Author's Kits, Supplier/Exhibit Information, Registration/Hotel Information, please contact:

IITC c/o Widerkehr & Associates, 19803 Laurel Valley Place, Montgomery Village, MD 20886 USA, Tel. +1-301-527-0900 x3, Fax. +1-301-527-0994, Email: iitchis.com